Post by Liu, Jinsong
This email provides 2 solutions for XSA-60 issue found by Konrad (refer attached email for XSA-60 please).
Basically it involves how to emulate guest setting cr0.cd. For shadow, as Jan pointed out in earlier email Xen drop all shadows so that any new ones would be created with UC memory type, _not_ involving iteration over the whole address space. For EPT, currently Xen traverse all ept entries via problematic set_uc_mode, resulting in DOS-like behavior, so this email focus on Intel EPT case.
Solution 1 is Dual-EPT tables: When guest setting cr0.cd trapped, stop using normal EPT, switch to a temp EPT table and populate new EPT entries w/ UC type on demand at later EPT violation. When guest clearing cr0.cd, switch back to normal EPT. In this way, _no_ unbounded loop involved and hence security hole avoided.
Some concerns for Dual-EPT: the 1st concern comes from cachablity confliction between guest and Xen memory type point of view, though it also exists in current implementation. The 2nd concern comes from Dual EPT tables inconsistency/sync issue: things become complicated when p2m modifying, PoD populating, and super page spliting, etc.
Solution 2 is via PAT emulation: For guest w/o VT-d, and for guest with VT-d but snooped, Xen need do nothing, just simply ignore guest setting cr0.cd, since hardware snoop mechanism has ensured cache coherency (under these cases currently Xen has set EPT iPAT bit, ignore guest's memory type opinion); For guest with VT-d but non-snooped, cache coherency can not be guaranteed by h/w snoop so guest's memory type opinion must be considered (under this case Xen set iPAT bit combining guest and host memory type opinion). Only under this case PAT emulation need set all IA32_PAT fields as UC so that guest memory type are all UC.
Concern for PAT solution still comes from cachablity confliction between guest and Xen.
BTW, today is Chinese National day, I will have several days travel with no email access, but your comments/suggestions are highly appreciated and I will reply ASAP after I come back.
Date: Wed, 24 Jul 2013 11:36:55 +0000
Subject: [Xen-devel] Xen Security Advisory 60 (CVE-2013-2212) - Excessive
time to disable caching with HVM guests with PCI passthrough
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Xen Security Advisory CVE-2013-2212 / XSA-60
Excessive time to disable caching with HVM guests with PCI passthrough
UPDATES IN VERSION 4
HVM guests are able to manipulate their physical address space such that
processing a subsequent request by that guest to disable caches takes an
extended amount of time changing the cachability of the memory pages assigned
to this guest. This applies only when the guest has been granted access to
some memory mapped I/O region (typically by way of assigning a passthrough
This can cause the CPU which processes the request to become unavailable,
possibly causing the hypervisor or a guest kernel (including the domain 0 one)
to halt itself ("panic").
For reference, as long as no patch implementing an approved alternative
solution is available (there's only a draft violating certain requirements
set by Intel's documentation), the problematic code is the function
vmx_set_uc_mode() (in that it calls ept_change_entry_emt_with_range() with
the full guest GFN range, which the guest has control over, but which also
would be a problem with sufficiently large but not malicious guests).
A malicious domain, given access to a device with memory mapped I/O
regions, can cause the host to become unresponsive for a period of
time, potentially leading to a DoS affecting the whole system.
Xen version 3.3 onwards is vulnerable.
Only systems using the Intel variant of Hardware Assisted Paging (aka EPT) are
This issue can be avoided by not assigning PCI devices to untrusted guests, or
by running HVM guests with shadow mode paging (through adding "hap=0" to the
domain configuration file).
Konrad Wilk found the issue as a bug, which on examination by the
Xenproject.org Security Team turned out to be a security problem.
There is currently no resolution to this issue.
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